(1) Field of the Invention
The present invention relates to semiconductor devices in general, and more particularly, to a method of forming shallow trench isolation (STI) without reverse short channel effect.
(2) Description of the Related Art
In STI art, it is often the case that when forming isolation trenches in semiconductor substrates, the corners of the trenches are undercut. Such undercutting can cause junction leakage and the associated undesirable phenomenon, which is sometimes referred to as xe2x80x9cKinkxe2x80x9d effect. It is disclosed later in the embodiments of the present invention a method of avoiding the formation of such undercuts, when fabricating shallow trench isolation.
Trench structures in semiconductors are employed for various purposes, such as for replacement of LOCOS (local oxidation of silicon) isolation for like devices within the same tub in a CMOS device, or for isolation of n-channel from p-channel devices, or as trench-capacitor structures in DRAMS, or for isolation of bipolar devices. Shallow refilled trenches are used primarily for isolating devices of the same type, and trench-capacitor structures are normally fabricated with narrow, deep trenches. By virtue of the shape of a trench, there usually results a sharp corner or shoulder where the trench intersects with the surface within which the trench is formed. Consequently, concentration of the electric-field occurs at the sharp corner region which in turn causes the lowering of the threshold voltage of the corner region, and this part of the device turns on at a lower voltage than does the interior portion of the device. As is known in the art, the problem is exacerbated if there is a downward step, i.e., undercut, in the field oxide adjacent the trench. The larger the step, the lower the threshold voltage, and unwanted subthreshold conduction begins at progressively lower values of the gate voltage. It is disclosed later in the embodiments of this invention a method of eliminating these common but undesirable steps, or, undercuts, at the trench corners and shoulders.
A conventional method of forming a shallow trench isolation is shown in prior art FIGS. 1a-1c. First, as shown in FIG. 1a, a substrate (10) is provided. Then, a pad oxide layer (20) is formed over substrate (10) using a thermal oxidation process. The pad oxide layer can be, for example, a silicon dioxide layer. Thereafter, silicon nitride (Si3N4) layer (30) is formed over the pad oxide layer using a low pressure chemical vapor deposition (LPCVD)) method.
Photoresist layer (40) is next formed, as shown in FIG. 1b, over silicon nitride layer (30), and then a photolithographic process is used to form a pattern on the silicon nitride layer (30). Then, silicon nitride layer (30) is anisotropically etched to expose portions of the pad oxide layer using a dry etching method. Similarly, using photoresist layer (40) and photolithographic processing again, a pattern is formed on the pad oxide layer (20) and substrate (10). Then, exposed pad oxide layer (20) is anisotropically etched by a dry etching method. Etching continues down into substrate (10), and finally forming a trench (18) having interior surfaces (55) that exposes portions of the substrate (10)
Next, as shown in FIG. 1c, photoresist layer (40) is removed to expose the silicon nitride layer. Then, a liner oxide layer (60) is formed at a high temperature using a thermal oxidation process. Liner oxide layer (60) covers the interior surfaces (55) of the trench (50), and has connection with pad oxide layer (20) at the top upper corner of trench (50).
In the conventional method, the thickness of both the liner oxide layer and the pad oxide layer is roughly the same. Therefore, due to the over-exposure of the substrate at the upper corner of the trench in a subsequent pad oxide layer removing process, an undercut as shown by reference numeral (65) in FIG. 1c leads to a Kink effect at the upper corner location. Hence, besides generating sub-threshold current in the device, a corner parasitic MOSFET will also be formed, leading to substantial current leakage in the device, hence reverse short channel effect.
In order to alleviate this type of Kink effect, Kuo et al, disclose in U.S. Pat. No. 6,025,249 a method of manufacturing a shallow trench isolation structure comprising the steps of forming a masking layer over a substrate; then, patterning the masking layer to form an opening; thereafter, forming an oxide layer over the surface of the masking layer and the opening; and, etching hack the oxide layer to form oxide spacers on the sidewalls of the masking layer. Subsequently, the substrate is etched downward along the side edges of the oxide spacers to form a trench. Thereafter, the oxide spacers are removed to expose the substrate surface formerly blocked by the oxide spacers. Finally, a liner oxide layer is formed on the trench surface over the substrate. In this manner, a smoother and thicker liner oxide layer is formed, and device current leakage due to subthreshold current and associated kink effect is avoided.
A different method of forming a shallow trench isolation is disclosed in U.S. Pat. No. 5,872,045 by Lou, et al. The method involves forming shallow trenches in a silicon substrate having a silicon nitride layer on the surface. After selectively oxidizing silicon exposed in the trenches, a second silicon nitride layer is deposited, and a composite polysilicon layer consisting of an undoped polysilicon layer and a gradient-doped polysilicon layer is deposited filling the trenches. The composite polysilicon layer is next chemical/mechanically polished back. The undoped polysilicon remaining in the trenches is then thermally oxidized to eliminate undercutting at the edges of the wide trenches, and the silicon nitride layers are removed by selectively etching to complete the shallow trench isolation.
Another method of forming isolation regions is shown in U.S. Pat. No. 5,834,358 by Pan et al., where they employ a silicon-comprising layer adjacent a trench during planarization of an oxide fill within the trench. An overhanging oxide sidewall is formed along a lateral edge of a trenched isolation region, the overhanging oxide sidewall overlapping an upper surface of a substrate immediately adjacent the trenched isolation region. An oxide plug is formed comprising a recessed portion below a substrate upper surface and an elevated portion above the substrate upper surface. The elevated portion comprising a ledge which extends over the substrate upper surface and has a top surface and a substantially vertical lateral edge side surface. Further, the plug may be within a substrate, the oxide plug having a recessed portion below a substrate upper surface and an elevated portion above the substrate upper surface, the elevated portion comprising a ledge extending over the substrate upper surface and abutting a polysilicon layer.
Still another method of forming an isolation oxide is disclosed in U.S. Pat. No. 5,677,233 where the oxide is formed from a silicon nitride layer deposited over a mask after removal of a side wall by using a polishing technique, thereby preventing the isolating oxide from undesirable undercutting during an etching step.
In the present invention, a method is described where the integrity of the trench edge, or, corner, is protected from unwanted process induced alterations by employing polyoxide spacers at said corner.
It is therefore an object of this invention to provide a method of forming a shallow isolation trench (STI) without kink effect.
It is another object of this invention to provide a method of forming an STI having reduced undercutting at the shoulder of the trench by protecting the trench edge with oxidized polysilicon spacers in the dielectric layers overlying the trench in the substrate.
It is yet another object of this invention to provide a method of forming an STI having reduced reverse short channel effect by employing polyoxide spacers above the trench edge and thermal oxide liner on the inside walls of the trench in the substrate.
These objects are accomplished by providing a substrate; forming a first oxide layer over said substrate; forming a nitride layer over said first oxide layer; forming a second oxide layer over said nitride layer; patterning said second oxide, said nitride and said first oxide layers to form an opening in said layers reaching the surface of said substrate; forming a conformal polysilicon layer over said substrate including over the inside walls of said opening; forming a polyoxide layer by oxidizing said polysilicon layer; forming polyoxide spacers along the vertical walls of said opening while at the same time etching away said polyoxide layer from the surface of said substrate and from the bottom wall of said opening, thus exposing the surface of said substrate; etching further said substrate through said opening to form a trench in said substrate; forming a thermal oxide liner over said substrate, including over said polyoxide spacers in said opening and over the inside walls of said trench; forming a trench oxide over said substrate, including over said opening and said trench in said substrate; planarizing said trench oxide; and stripping said second oxide, nitride and said first oxide layers to form said shallow trench isolation of the invention.